head	1.5;
access;
symbols;
locks; strict;
comment	@# @;


1.5
date	99.01.30.21.07.43;	author ryu;	state Exp;
branches;
next	1.4;

1.4
date	99.01.29.06.21.26;	author ryu;	state Exp;
branches;
next	1.3;

1.3
date	99.01.29.05.16.22;	author ryu;	state Exp;
branches;
next	1.2;

1.2
date	99.01.28.07.05.38;	author ryu;	state Exp;
branches;
next	1.1;

1.1
date	99.01.27.16.33.34;	author ryu;	state Exp;
branches;
next	;


desc
@*	$Id: dff_2x.sp,v 1.4 1999/01/21 08:11:40 ryu Exp $
@


1.5
log
@resized
@
text
@*	$Id: dffce_2x.sp,v 1.4 1999/01/29 06:21:26 ryu Exp ryu $

.subckt xgate out in gaten gatep
+	wp=4
+	wn=2
m0 in gatep out vdd pch l=0.35 w=wp
m1 in gaten out gnd nch l=0.35 w=wn
.ends

.subckt inv out in
+	wp=12
+	wn=6
m0 out in gnd gnd nch l=0.35 w=wn
m1 out in vdd vdd pch l=0.35 w=wp
.ends

.subckt dff_2x q d clk clk_n
* Begin port declarations
* port output q
* port input d
* port input clk
* port input clk_n
* End port declarations
x1 min d clk_n clk xgate
x2 min mout inv wp=2 wn=1
x3 mout min inv
x4 s mout clk clk_n xgate
x5 s s_n inv wp=2 wn=1
x6 s_n s inv
x7 q s inv
cmin min gnd 5fF
cmout mout gnd 5fF
cs s gnd 5fF
cs_n s_n gnd 5fF
.ends

.subckt mux2 out s0 i0 i1
* Begin port declarations
* port output out
* port input s0
* port input i0
* port input i1
* End port declarations
x0 n1 i0 s0 s0_n xgate wp=6 wn=3
x1 n1 i1 s0_n s0 xgate wp=6 wn=3
x2 s0_n s0 inv wp=6 wn=3
x3 out_n n1 inv wp=10 wn=5
x4 out out_n inv wp=10 wn=5
.ends

.subckt dffce_2x q d ce clk clk_n
* Begin port declarations
* port output q
* port input d
* port input ce
* port input clk
* port input clk_n
* End port declarations
xdff q d0 clk clk_n dff_2x
xmux2 d0 ce d q mux2
.ends

@


1.4
log
@typo
@
text
@d1 1
a1 1
*	$Id: dffce_2x.sp,v 1.3 1999/01/29 05:16:22 ryu Exp ryu $
d4 2
a5 2
+	wp=10.0
+	wn=5.0
d11 2
a12 2
+	wp=10
+	wn=5
@


1.3
log
@wip
@
text
@d1 1
a1 1
*	$Id: dffce_2x.sp,v 1.2 1999/01/28 07:05:38 ryu Exp ryu $
d48 1
a48 1
x3 out out_n inv wp=10 wn=5
@


1.2
log
@hand editted
@
text
@d1 1
a1 1
*	$Id: dffce_2x.sp,v 1.1 1999/01/27 16:33:34 ryu Exp ryu $
d27 1
a27 1
x4 s mout clk clk_n XGATE
d60 1
a60 1
xmux2 d0 ce d q
@


1.1
log
@entered into RCS
@
text
@d1 1
a1 1
*	$Id: dff_2x.sp,v 1.4 1999/01/21 08:11:40 ryu Exp $
d3 1
a3 1
.subckt XGATE out in gaten gatep
d10 1
a10 1
.subckt INV out in
d17 1
a17 1
.subckt DFF_2X q d clk clk_n
d24 3
a26 3
x1 min d clk_n clk XGATE
x2 min mout INV wp=2 wn=1
x3 mout min INV
d28 3
a30 3
x5 s s_n INV wp=2 wn=1
x6 s_n s INV
x7 q s INV
d37 1
a37 1
.subckt MUX2N out s0 i0 i1
d44 5
a48 4
x0 n1 i0 s0 s0_n XGATE wp=6 wn=3
x1 n1 i1 s0_n s0 XGATE wp=6 wn=3
x2 out n1 INV wp=10 wn=5
x3 s0_n s0 INV wp=6 wn=3
d51 1
a51 1
.subckt DFFCE_2X q d ce clk clk_n
d59 2
a60 2
xdff q_n d_n clk clk_n DFF_2X
xmux2 d_n ce d q
@