#	$Id: TODO,v 1.10 1999/02/09 13:16:32 ryu Exp $
 
#	Copyright (C) 1999 Robert K. Yu
#	email: robert@yu.org
 
#	This file is part of Autochar.
 
#	Autochar is free software; you can redistribute it and/or modify
#	it under the terms of the GNU General Public License as published by
#	the Free Software Foundation; either version 2, or (at your option)
#	any later version.
 
#	Autochar is distributed in the hope that it will be useful,
#	but WITHOUT ANY WARRANTY; without even the implied warranty of
#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#	GNU General Public License for more details.
 
#	You should have received a copy of the GNU General Public License
#	along with Autochar; see the file COPYING.  If not, write to the
#	Free Software Foundation, Inc., 59 Temple Place - Suite 330,
#	Boston, MA 02111-1307, USA.
 
 
x	Get port order from spice
	Get port direction from verilog
 
x	Handle differential, equivalent.
 
x	cin: optimization
x	setup/hold: use hspice bisect
x	    - look at internal node
	    - do not look at internal node
x	clock_q
	power
	path delay module (from static timing output)
	tristate buffer
	device characterization
 
x	Generate synopsys lib format
	Generate html datasheets
 
?	tcl GUI interface
-	Load defaults
	Error checking
	    spice run error, aborts
	    terminal existence check
 
x	Slew rate from exp source instead of slewbuffer.
x	Add resistor for buffer for inputcap.
	Setup/Hold using 5% deviation from idea clock-q time
	    as criterion.
 
x	slew rate dependence on setup/hold
x	output linear or nonlinear models (clock-q only)
x	index list for nonlinear models -> using lu_table_name
 
 
Key:
    x = done
    ? = propably not worth doing
    - = changed my mind