head 1.13; access; symbols IPX_C21:1.5.2.2 ce_phy-A0-combophy-150401-R25_000:1.5.2.2 ce_phy-A0-usb30_phy-150223-R16_000:1.13 ce_phy-A0-usb30_phy-150213-R15_000:1.11 PCIE_MULTILANE:1.5.2.2 ce_phy-A0-combophy-150128-R24_000:1.5.2.2 ce_phy-A0-combophy-150123-R23_000:1.5.2.2 ce_phy-A0-usb30_phy-150120-R14_000:1.11 ce_phy-A0-combophy-150114-R22_000:1.5.2.2 ce_phy-A0-usb30_phy-150109-R13_000:1.11 ce_phy-A0-usb30_phy-141216-R12_000:1.10 ce_phy-A0-usb30_phy-141209-R11_000:1.10 ce_phy-A0-combophy-141209-R21_000:1.5.2.2 ce_phy-A0-combophy-141205-R20_000:1.5.2.2 ce_phy-A0-usb30_phy-141205-R10_000:1.10 ce_phy-B0-combophy-141111-R00_000:1.5.2.2 BCM7439_B0_TAPEOUT:1.5.2.2 IPX_C20:1.5.2.2 ce_phy-B0-usb30_phy-141105-R00_000:1.10 IPX_C19:1.5.2.2 ce_phy-A0-usb30_phy-141030-R09_000:1.10 IPX_C18:1.5.2.2 ce_phy-A0-usb30_phy-141014-R08_000:1.9 IPX_C17:1.5.2.2 IPX_C16:1.5.2.2 ce_phy-A0-usb30_phy-140820-R07_000:1.9 ce_phy-A0-usb30_phy-140813-R06_000:1.9 VULCAN_IPX_A0:1.9 WB_1PORT_IPX_B4:1.5.2.2 WB_1PORT_IPX_B3:1.5.2.2 WB_1PORT_IPX_B2:1.5.2.2 WB_1PORT_IPX_B1:1.5.2.2 WB_1PORT_IPX_B0:1.5.2.2 BCM63381_B0_TAPEOUT:1.5.2.2 IPX_C15:1.5.2.2 IPX_C14:1.5.2.2 IPX_C13:1.5.2.2 IPX_C12:1.5.2.2 IPX_C11:1.5.2.2 IPX_C10:1.5.2.2 IPX_C9:1.5.2.2 IPX_B28:1.4 IPX_B27:1.4 ce_phy-A0-combophy-140724-R19_000:1.5.2.2 ce_phy-A0-combophy-140720-R18_000:1.5.2.2 ce_phy-A0-combophy-140617-R17_000:1.5.2.2 ce_phy-A0-combophy-140612-R16_000:1.5.2.2 ce_phy-A0-combophy-140523-R15_000:1.5.2.2 ce_phy-A0-combophy-140509-R14_000:1.5.2.2 ce_phy-A0-combophy-140430-R13_000:1.5.2.2 ce_phy-A0-combophy-140425-R12_000:1.5.2.2 ce_phy-A0-combophy-140424-R11_000:1.5.2.2 ce_phy-A0-combophy-140413-R10_000:1.5.2.2 ce_phy-A0-combophy-140408-R09_000:1.5.2.2 IPX_C8:1.5.2.2 IPX_C7:1.5.2.2 ce_phy-A0-combophy-140315-R08_000:1.5.2.2 ce_phy-A0-usb30_phy-140309-R05_000:1.9 IPX_C6:1.5.2.2 ce_phy-A0-usb30_phy-140228-R04_000:1.9 ce_phy-A0-combophy-140228-R07_000:1.5.2.2 VULCAN_IPX_A1:1.9 ce_phy-A0-combophy-140224-R06_000:1.5.2.2 BCM7445_D0_TAPEOUT:1.4 ce_phy-A0-combophy-140218-R05_000:1.5.2.2 ce_phy-A0-combophy-140213-R04_000:1.5.2.2 ce_phy-A0-combophy-140212-R03_000:1.5.2.2 IPX_B26:1.4 IPX_C5:1.5.2.2 ce_phy-A0-combophy-140203-R02_000:1.5.2.2 ce_phy-A0-combophy-140131-R01_000:1.5.2.2 IPX_C4_PATCH1:1.5.2.2 IPX_C4:1.5.2.2 IPX_C3:1.5.2.2 ce_phy-A0-usb30_phy-140109-R03_000:1.5.2.2 IPX_C2:1.5.2.2 BCM63148_A0_TAPEOUT:1.4 IPX_B25:1.4 ce_phy-A0-usb30_phy-140102-R02_000:1.5.2.2 Prelim_Synthesis_working:1.8 ce_phy-A0-usb30_phy-131219-R01_000:1.5.2.2 IPX_C1:1.5.2.2 MALTA_IPX_A7:1.8 ce_phy-A0-usb30_phy-131212-R00_000:1.5.2.2 ce_phy-A0-usb30phy-131208-R01_000:1.5.2.2 IPX_B24:1.4 ce_phy-A0-usb30phy-131206-R00_000:1.5.2.2 IPX_B23:1.4 IPX_B22:1.4 IPX_B21:1.4 FC_1PORT_IPX_A2:1.5.2.2 IPX_B20:1.4 FC_1PORT_IPX_A1:1.5.2.2 MALTA_IPX_A6:1.7 IPX_B19:1.4 FC_1PORT_IPX_A0:1.5.2.1 IPX_B18:1.4 IPX_B17:1.4 BCM63381_A0:1.5.0.2 BCG_28NM:1.5.0.2 BCM63381_A0_TAPEOUT:1.5 WB_1PORT_IPX_A7:1.5 WB_1PORT_IPX_A6:1.5 WB_1PORT_IPX_A5:1.5 MALTA_IPX_A5:1.7 MALTA_IPX_A4:1.7 PRE_POWER_SWITCHES:1.7 WB_1PORT_IPX_A4:1.5 WB_1PORT_IPX_A3:1.5 MALTA_IPX_A3:1.7 WB_1PORT_IPX_A2:1.5 BCM63138_A0_TAPEOUT:1.4 IPX_B16:1.4 IPX_B15:1.4 MALTA_IPX_A2:1.6 IPX_B14:1.4 MALTA_IPX_A1:1.5 PRE_MALTA:1.5 IPX_B13:1.4 IPX_B12:1.4 IPX_B11:1.4 BCM63138/BCM7439_A0:1.4.0.4 WB_1PORT_IPX_A1:1.5 PRE_63381:1.4 IPX_B10:1.4 IPX_B9:1.4 IPX_B8:1.4 IPX_B7:1.4 IPX_B6:1.4 IPX_B5:1.4 IPX_B4:1.4 malta_20nm:1.4.0.2 BCM7445_IPX_A14_patch0:1.3 IPX_A22:1.3 IPX_B3:1.4 BCM7445_A0_TAPEOUT:1.3 IPX_A21:1.3 IPX_A20:1.3 IPX_A19:1.3 IPX_B2:1.3 IPX_B1:1.3 IPX_B0:1.3 NEW_RXPMD_INIT:1.3 IPX_A18:1.3 IPX_A17:1.3 IPX_A16:1.3 IPX_A15:1.3 BCM7445_IPX_A14:1.3 BCM7445_IPX_A13:1.3 BCM7445_IPX_A12:1.3 BCM7445_IPX_A11:1.3 BCM7445_IPX_A10:1.3 BCM7445_IPX_A9:1.3 BCM7445_IPX_A8:1.3 BCM7445_IPX_A7:1.3 BCM7445_IPX_A6:1.2 BCM7445_IPX_A5:1.2 BCM7445_IPX_A4:1.2 BCM7445_IPX_A3:1.2 OLD_SLICER_CAL:1.2 PHASE_ENC_THERM:1.2 BCM7445_IPX_A2:1.2 BCM7445_IPX_A1:1.1 BCM7445_IPX_A0:1.1; locks; strict; comment @# @; 1.13 date 2015.02.15.01.46.55; author zluo; state Exp; branches; next 1.12; commitid U5a4ri5XzrAHP2ay; 1.12 date 2015.02.12.02.09.53; author zluo; state Exp; branches; next 1.11; commitid 074rZffpnXGy3F9y; 1.11 date 2015.01.09.18.06.57; author jerryp; state Exp; branches; next 1.10; commitid 6car5kGr1CoErn5y; 1.10 date 2014.10.31.01.00.40; author jerryp; state Exp; branches; next 1.9; commitid k5ZMwkQhuUE41iWx; 1.9 date 2014.02.28.18.26.38; author sharathk; state Exp; branches; next 1.8; 1.8 date 2013.12.13.23.24.16; author jerryp; state Exp; branches; next 1.7; 1.7 date 2013.07.01.23.15.18; author jerryp; state Exp; branches; next 1.6; 1.6 date 2013.05.31.21.30.26; author jerryp; state Exp; branches; next 1.5; 1.5 date 2013.04.23.00.00.37; author jerryp; state Exp; branches 1.5.2.1; next 1.4; 1.4 date 2013.01.22.21.09.10; author anilj; state Exp; branches; next 1.3; 1.3 date 2012.08.11.00.45.42; author jerryp; state Exp; branches; next 1.2; 1.2 date 2012.06.28.22.45.12; author jerryp; state Exp; branches; next 1.1; 1.1 date 2012.06.14.22.00.34; author jerryp; state Exp; branches; next ; 1.5.2.1 date 2013.08.27.01.15.13; author jerryp; state Exp; branches; next 1.5.2.2; 1.5.2.2 date 2013.09.11.01.06.57; author jerryp; state Exp; branches 1.5.2.2..1; next ; 1.5.2.2..1 date 2015.02.15.01.14.59; author zluo; state Exp; branches; next ; commitid pBg1G8EVuEgKE2ay; desc @@ 1.13 log @roll back to r.11. The change is in a combo-phy branch @ text @//----------------------------------------------------------------- // // Author :kkishore // Language :verilog // First Created On :Fri Sep 3 16:31:30 PDT 2010 // //----------------------------------------------------------------- //----------------------------------------------------------------- // DESCRIPTION: top-level MDIO register read/write control //----------------------------------------------------------------- // $Log: usb30_phy_mdio.sv,v $ // Revision 1.11 2015/01/09 18:06:57 jerryp // add csr_mdio_ssc_en output and set SSC_BLOCK_ADDR to 0x801 // // Revision 1.10 2014/10/31 01:00:40 jerryp // change usb20_scan_pllmux instance to usb30_scan_pllmux instance // // Revision 1.9 2014/02/28 18:26:38 sharathk // initial revision for vulcan, use usb30_phy.sv as top and use 16nm std cells // // Revision 1.8 2013/12/13 23:24:16 jerryp // define reg_dout assignment for VIPER20 by removing dout for pmd, pll, afe30 // add analog_mdout input and OR it into reg_dout assignment for VIPER20 // // Revision 1.7 2013/07/01 23:15:18 jerryp // remove reg_din and reg_write wires to eliminate synthesis warnings // remove illegal `USB3_CKBUFX12 instances and replace with usb30_clkbuf // remove unnecessary ports, reg, and parameters that were defined in phy_csr // // Revision 1.6 2013/05/31 21:30:26 jerryp // add csr_mdio_afe20_dout input and add csr_mdio_afe20_dout to reg_dout assign // // Revision 1.5 2013/04/23 00:00:37 jerryp // change reg_dout assignment for 1-port to only use dout[0] // // Revision 1.4 2013/01/22 21:09:10 anilj // "Moved mdio_wrclk_tree_inst from output of MUX to i0 of MUX" // // Revision 1.3 2012/08/11 00:45:42 jerryp // change (afe30, dfe30, rxpmd, txpmd)_dout inputs to support multiple pipes // change reg_dout assignment to include dout from both pipe 0 and pipe 1 // // Revision 1.2 2012/06/28 22:45:12 jerryp // add mdio_mode output so it can be used by vco_pllReg and other mdio blocks // change csr_mdio_rxpmd_aeq_en block enable from one bit to two bits // add SLCAL_BLOCK_ADDR and use it to enable csr_mdio_rxpmd_aeq_en[1] // // Revision 1.1 2012/06/14 22:00:34 jerryp // initial revision // // Revision 1.12 2012/05/16 02:33:55 kkishore // fixed txdeemphais for CP6 and CP8 // // Revision 1.11 2012/05/11 02:21:21 kkishore // added txclk2rxclk mux in the clkgen block // // Revision 1.10 2012/05/10 22:56:54 kkishore // fixed typo in phy_status30 assignment // // Revision 1.9 2011/12/20 21:39:22 kkishore // changed all std cell prefix to USB3 // // Revision 1.8 2011/12/20 18:23:47 kkishore // changed drive strength of CK cells // // Revision 1.7 2011/11/15 01:23:37 kkishore // bringing out scanable mdio clock out // // Revision 1.6 2011/11/02 21:32:33 kkishore // added tx_lpen and tx_lsen // // Revision 1.5 2011/10/10 20:02:22 kkishore // changed p1_exit time to 200ns // // Revision 1.4 2011/08/22 18:48:22 kkishore // minor update // // Revision 1.3 2011/08/19 18:52:00 kkishore // added prbs_rxerrclr signal // // Revision 1.2 2011/08/13 00:36:42 kkishore // fixed AFE30 reads block address // // Revision 1.1.1.1 2011/07/13 06:24:06 kkishore // Initial import of USB3/PCIe2 combo PHY design // // Revision 1.4 2011/06/14 22:56:32 kkishore // added refclkpd_p2enable and refclkpd_p3enable signals // // Revision 1.3 2011/06/13 21:59:41 kkishore // updated due to bug fixes // // Revision 1.2 2011/05/19 22:15:41 kkishore // added AEQ block enable // // Revision 1.1.1.1 2011/04/25 23:51:46 kkishore // // Initial import of usb30phy testchip data // // Revision 1.2 2011/02/23 20:14:07 kkishore // corrected missing comment delimiters // // Revision 1.1.1.1 2011/02/23 18:03:18 kkishore // initial import for 40lp testchip module usb30_phy_mdio # (parameter NUM_USB30_PORTS = 2) ( // top-level signals input scan_testmode, // scan testmode input scan_lv_mode, // scan test in logicbist mode input scan_atspeed_mode, // scan test in at-speed mode input scan_clk, // scan clock input scan_enable, // scan enable // external MDIO port input [4:0] mdio_id_i, // MDIO ID, strap signal input mdio_clk_i, input mdio_resetb_i, input mdio_data_i, output mdio_data_o, output mdio_data_en_o, // for scan output mdio_clk, output mdio_mode, // top-level signals input [15:0] tp_sel_i, output [15:0] csr_tp_sel, output [NUM_USB30_PORTS - 1:0] csr_mdio_afe30_en, output [NUM_USB30_PORTS - 1:0] csr_mdio_dfe30_en, output [NUM_USB30_PORTS - 1:0] csr_mdio_afe20_en, output [NUM_USB30_PORTS - 1:0] csr_mdio_dfe20_en, // VCO/RXPMD/TXPMD block register bus signals output reg_write, output [15:0] reg_din, output [4:0] csr_mdio_addr, output csr_mdio_clr, output csr_mdio_wr, output csr_mdio_rd, output [15:0] csr_mdio_din, input [15:0] analog_mdout, // MDIO read data from afe input [NUM_USB30_PORTS - 1:0][15:0] csr_mdio_afe20_dout, input [NUM_USB30_PORTS - 1:0][15:0] csr_mdio_afe30_dout, input [NUM_USB30_PORTS - 1:0][15:0] csr_mdio_dfe30_dout, input [15:0] csr_mdio_pll_dout, output csr_mdio_pll_en, output csr_mdio_ssc_en, input [NUM_USB30_PORTS - 1:0][15:0] csr_mdio_rxpmd_dout, output [NUM_USB30_PORTS - 1:0] csr_mdio_rxpmd_en, output [NUM_USB30_PORTS - 1:0] [1:0] csr_mdio_rxpmd_aeq_en, input [NUM_USB30_PORTS - 1:0][15:0] csr_mdio_txpmd_dout, output [NUM_USB30_PORTS - 1:0] csr_mdio_txpmd_en ); // internal signals wire [4:0] reg_addr; wire [15:0] reg_dout; wire reg_read; reg [15:0] mdio_write_data; reg [15:0] mdio_mode_write; reg [15:0] test_port_write; reg [15:0] base_addr_write; parameter MDIO_MODE_ADDR = 5'h1d, // make sure there is no 1D register in block registers TEST_PORT_ADDR = 5'h1e, // make sure there is no 1E register in block registers REG_BLOCK_ADDR = 5'h1f, // make sure there is no 1F register in block registers PLL30_BLOCK_ADDR = 12'h800, SSC_BLOCK_ADDR = 12'h801, RXPMD_BLOCK_ADDR = 12'h802, TXPMD_BLOCK_ADDR = 12'h804, DFE30_BLOCK_ADDR = 12'h806, AFE30_BLOCK_ADDR = 12'h808, DFE20_BLOCK_ADDR = 12'h80a, AFE20_BLOCK_ADDR = 12'h80c, AEQ30_BLOCK_ADDR = 12'h80e, SLCAL_BLOCK_ADDR = 12'h80f; usb30_scan_pllmux u_usb30_scan_pllmux_MDIO (.i_func_clk (mdio_clk_i), .i_atspeed_test_clk (mdio_clk_i), .i_scan_clk (scan_clk), .i_scan_enable (scan_enable), .i_scan_testmode (scan_testmode), .i_scan_pll_clock_en (scan_atspeed_mode), .i_scan_lv_mode (scan_lv_mode), .o_func_test_clk (mdio_clk_scan) ); usb30_clkbuf MDIO_CLK_tree_inst (.i(mdio_clk_scan), .o(mdio_clk)); // Instantiation of MDIO slave block usb30_mdio_slave u_usb30_mdio_slave ( // mdio port interface signals .mdio_id_i (mdio_id_i), .mdio_clk_i (mdio_clk), .mdio_resetb_i (mdio_resetb_i), .mdio_data_i (mdio_data_i), .mdio_data_o (mdio_data_o), .mdio_data_en_o (mdio_data_en_o), // reg interface signals .reg_dout (reg_dout), // MDIO read data .reg_addr (reg_addr), .reg_din (reg_din), // MDIO write data .reg_write (reg_write), .reg_read (reg_read) ); // hold the mdio write data always @@ (posedge mdio_clk, negedge mdio_resetb_i) begin if (!mdio_resetb_i) mdio_write_data <= 16'h0000; else if (reg_write) mdio_write_data <= reg_din; end // always // delay the register write enable // `USB3_DLY1000X3 mdio_wrclk_delay_inst (.i(reg_write), .o(reg_write_delay)); `USB3_DLY200X3 mdio_wrclk_delay_inst_0 (.i(reg_write), .o(reg_write_delay1)); `USB3_DLY200X3 mdio_wrclk_delay_inst_1 (.i(reg_write_delay1), .o(reg_write_delay2)); `USB3_DLY200X3 mdio_wrclk_delay_inst_2 (.i(reg_write_delay2), .o(reg_write_delay3)); `USB3_DLY200X3 mdio_wrclk_delay_inst_3 (.i(reg_write_delay3), .o(reg_write_delay4)); `USB3_DLY200X3 mdio_wrclk_delay_inst_4 (.i(reg_write_delay4), .o(reg_write_delay)); `USB3_CKMUX2X8 mdio_wrclk_scanmux_dont_touch (.i0(~reg_write_delay), .i1(mdio_clk), .sel(scan_testmode), .o(mdio_wrclk_scan)); usb30_clkbuf mdio_wrclk_tree_inst (.i(mdio_wrclk_scan), .o(mdio_wrclk)); //--------------------------------------------------------------------- // direct registers - write operation //--------------------------------------------------------------------- always @@ (posedge mdio_clk, negedge mdio_resetb_i) begin if (!mdio_resetb_i) begin mdio_mode_write <= 16'h0000; // mdio mode register test_port_write <= 16'h0000; // test port register for real-time debug base_addr_write <= 16'h0000; // base address of register blocks end else begin if ((reg_addr == MDIO_MODE_ADDR) & reg_write) mdio_mode_write <= reg_din; if ((reg_addr == TEST_PORT_ADDR) & reg_write) test_port_write <= reg_din; if ((reg_addr == REG_BLOCK_ADDR) & reg_write) base_addr_write <= reg_din; end end // always //--------------------------------------------------------------------- // direct registers - read operation //--------------------------------------------------------------------- wire [15:0] mdio_mode_read = ((reg_addr == MDIO_MODE_ADDR) & reg_read)? mdio_mode_write : 16'h0000; wire [15:0] test_port_read = ((reg_addr == TEST_PORT_ADDR) & reg_read)? test_port_write : 16'h0000; wire [15:0] base_addr_read = ((reg_addr == REG_BLOCK_ADDR) & reg_read)? base_addr_write : 16'h0000; wire mdio_mode = mdio_mode_write[0]; assign csr_tp_sel = mdio_mode? test_port_write : tp_sel_i; //--------------------------------------------------------------------- // block register mdio connections //--------------------------------------------------------------------- assign csr_mdio_addr = reg_addr; assign csr_mdio_clr = 1'b0; assign csr_mdio_wr = mdio_wrclk; assign csr_mdio_rd = reg_read; assign csr_mdio_din = mdio_write_data; assign csr_mdio_pll_en = (base_addr_write[15:4] == PLL30_BLOCK_ADDR); // PLL block registers enable assign csr_mdio_ssc_en = (base_addr_write[15:4] == SSC_BLOCK_ADDR); // SSC block registers enable genvar gi; generate for(gi=0; gi 1) assign reg_dout = mdio_mode_read | test_port_read | base_addr_read | analog_mdout | csr_mdio_afe20_dout[0] | csr_mdio_dfe30_dout[0] | csr_mdio_afe20_dout[1] | csr_mdio_dfe30_dout[1]; else assign reg_dout = mdio_mode_read | test_port_read | base_addr_read | analog_mdout | csr_mdio_afe20_dout[0] | csr_mdio_dfe30_dout[0]; endgenerate `else generate if (NUM_USB30_PORTS > 1) assign reg_dout = mdio_mode_read | test_port_read | base_addr_read | csr_mdio_pll_dout | csr_mdio_rxpmd_dout[0] | csr_mdio_txpmd_dout[0] | csr_mdio_afe20_dout[0] | csr_mdio_afe30_dout[0] | csr_mdio_dfe30_dout[0] | csr_mdio_rxpmd_dout[1] | csr_mdio_txpmd_dout[1] | csr_mdio_afe20_dout[1] | csr_mdio_afe30_dout[1] | csr_mdio_dfe30_dout[1]; else assign reg_dout = mdio_mode_read | test_port_read | base_addr_read | csr_mdio_pll_dout | csr_mdio_rxpmd_dout[0] | csr_mdio_txpmd_dout[0] | csr_mdio_afe20_dout[0] | csr_mdio_afe30_dout[0] | csr_mdio_dfe30_dout[0]; endgenerate `endif endmodule // usb30_phy_mdio @ 1.12 log @add pcie register bank, replace afe20 by sata @ text @d136 1 a137 2 output [NUM_USB30_PORTS - 1:0] csr_mdio_sata_en, output [NUM_USB30_PORTS - 1:0] csr_mdio_pcie_en, d186 1 a186 2 SATA_BLOCK_ADDR = 12'h80c, PCIE_BLOCK_ADDR = 12'h80d, d303 1 a303 2 assign csr_mdio_sata_en[gi] = (base_addr_write[15:4] == SATA_BLOCK_ADDR + (gi * 12'h100)); // SATA block registers enable assign csr_mdio_pcie_en[gi] = (base_addr_write[15:4] == PCIE_BLOCK_ADDR + (gi * 12'h100)); // PCIE block registers enable @ 1.11 log @add csr_mdio_ssc_en output and set SSC_BLOCK_ADDR to 0x801 @ text @d13 3 a135 1 output [NUM_USB30_PORTS - 1:0] csr_mdio_afe20_en, d137 2 d187 2 a188 1 AFE20_BLOCK_ADDR = 12'h80c, d305 2 a306 1 assign csr_mdio_afe20_en[gi] = (base_addr_write[15:4] == AFE20_BLOCK_ADDR + (gi * 12'h100)); // AFE20 block registers enable @ 1.10 log @change usb20_scan_pllmux instance to usb30_scan_pllmux instance @ text @d13 3 d152 1 d177 1 d287 1 @ 1.9 log @initial revision for vulcan, use usb30_phy.sv as top and use 16nm std cells @ text @d13 3 d182 1 a182 1 usb20_scan_pllmux u_usb20_scan_pllmux_MDIO (.i_func_clk (mdio_clk_i), @ 1.8 log @define reg_dout assignment for VIPER20 by removing dout for pmd, pll, afe30 add analog_mdout input and OR it into reg_dout assignment for VIPER20 @ text @d13 4 d224 6 a229 1 `USB3_DLY1000X3 mdio_wrclk_delay_inst (.i(reg_write), .o(reg_write_delay)); @ 1.7 log @remove reg_din and reg_write wires to eliminate synthesis warnings remove illegal `USB3_CKBUFX12 instances and replace with usb30_clkbuf remove unnecessary ports, reg, and parameters that were defined in phy_csr @ text @d13 5 d135 1 a285 1 d287 20 d334 1 @ 1.6 log @add csr_mdio_afe20_dout input and add csr_mdio_afe20_dout to reg_dout assign @ text @d13 3 a110 5 input pipe_txswing, // 1'b0: Full swing; 1'b1: Half swing input [3:0] pipe_txmargin, // this is valid only when pipe_txmargin_en=1 input pipe_txmargin_en, // tx margin enable input [4:0] pipe_txdeemph, // this is valid only when pipe_txdeemph_en=1 input pipe_txdeemph_en, // tx de-emphasis enable d142 1 a142 100 output [NUM_USB30_PORTS - 1:0] csr_mdio_txpmd_en, // AFE30 status signals input [31:0] phy_status30, // PIPE block signals input [9:0] sync_pos, // symbol position during symbol lock operation input [3:0] sync_state, // sync block state input sync_lock, // symbol lock; high means locked input sync_pol, // symbol polarity when locked input [63:0] prbs_error, // PRBS error input [15:0] prbs_status, // PRBS status output sync_track, // tracking enable for symbol tracking output skip_align, // symbol alignment enable output skip_override, // does not add/remove SKIPs, FIFO over/underflows output [5:0] skip_maxth, // SKIP max level for elastic buffer (default is 6'b00_1100) output [5:0] skip_halfth, // SKIP half level for elastic buffer (default is 6'b00_0111) output [5:0] skip_minth, // SKIP min level for elastic buffer (defaut is 6'b00_0010) output lnktraining, // indicates TSEQ/TS1/TS2 output [7:0] symb_error_max, // maximum symbol/disparity errors that are allowed to go out of comma lock output txdisparityInit, // iniital tx disparity output [7:0] lfps_cmpmaxth, // LFPS detection max threshold; default 8'hf6 (-10) output [7:0] lfps_cmpminth, // LFPS detection min threshold; default 8'h0a (+10) output [2:0] lfps_deglmaxth, // LFPS de-glitch threshold; default 3'b100 output [2:0] lfps_deglminth, // LFPS de-glitch threshold; default 3'b010 output [4:0] comppat_width, // 1's and 0's width of compliance patterns; it must be between 4 and 24 10T clocks output [15:0] lfck_width, // LFCK clock period width output [15:0] time_p1_entry, // P1 entry time from P0 output [15:0] time_p2_entry, // P2 entry time from P0 or P1 output [15:0] time_p3_entry, // P3 entry time from P0, based on refclk or auxclk output [15:0] time_p1_exit, // timer for P1 to P0 output [15:0] time_p2_exit, // timer for P2 to P0 output [15:0] time_p3_exit, // timer for P3 to P0 based on refclk or auxclk output [4:0] lfps_width, // LFPS pulse width; period = 2*pulse_width output csr_tx_lpen, // TX low-power mode enable output csr_tx_lsen, // TX low-swing mode enable output refclkpd_p2enable, // refclk ckt pd in p2 output refclkpd_p3enable, // refclk ckt pd in p3 output txpwrdn_p3enable, output [9:0] rxterm_timeout, // RXTERM detection timeout output prbs_txclk2rxclk, // muxes the txclk10 into rxclk10, to be used in gloop mode output prbs_rxerrclr, // prbs error count clear output prbs_rxstart, // enables the start of PRBS detection; can have multiple starts within once enabled output rloop_enable, // RX -> TX loop enable output gloop_enable, // TX -> RX loop enable output prbs_enable, // enables the PRBS output prbs_txstart, // enables the start of PRBS sequence; can have multiple starts within once enabled output [1:0] prbs_order, // 2'b00: 7th order, 2'b01: 15th order, 2'b10: 23rd order, 2'b11: 31th order polynomial output prbs_inv, // inverted polarity output prbs_mode, // 1'b0: random, 1'b1: fixed output prbs_width, // prbs data word width; 1'b0: 32-bits, 1'b1: 10-bits output prbs_burst, // prbs burst mode/continuous mode output [31:0] prbs_seed, // inital seed value output [31:0] prbs_pkt, // number of packets output [15:0] prbs_size, // bytes per packet output [15:0] prbs_ipg, // inter-packet gap // USB20 (AFE+DFE) signals input [15:0] phy_p1ctl_i, input [15:0] phy_p2ctl_i, input [15:0] phy_p3ctl_i, input [15:0] phy_p4ctl_i, input [2:0] pll_pdiv_i, // PLL Pre-divider (divides ref_clk to get in to a known range) input [9:0] pll_ndiv_int_i, // PLL Feedback-divider (This controls the VCO frequency) input [2:0] pll_ka_i, // PLL loop-gain, default to 3'b011 input [2:0] pll_ki_i, // PLL P/I loop filter integrator path gain, default to 3'b011 input [3:0] pll_kp_i, // PLL P/I loop filter proportional path gain, default to 4'b1010 input pll_resetb_i, // PLL reset, active-low input pll_suspend_en_i, // PLL will be ON during suspend mode when high input [28:0] afe_sts_cdm, input [31:0] bert_sts1, input [31:0] bert_sts2, input [31:0] phy_status20, // PHY status bits output [15:0] csr_p1ctl, output [15:0] csr_p2ctl, output [15:0] csr_p3ctl, output [15:0] csr_p4ctl, output [15:0] csr_usb11, output [2:0] csr_pll_pdiv, // PLL Pre-divider (divides ref_clk to get in to a known range) output [9:0] csr_pll_ndiv_int, // PLL Feedback-divider (This controls the VCO frequency) output [2:0] csr_pll_ka, output [2:0] csr_pll_ki, output [3:0] csr_pll_kp, output csr_pll_resetb, // PLL reset, active-low output csr_pll_suspend_en, // PLL will be ON during suspend mode when high output [31:0] csr_bert_cfg1, // bert configuration bits output [31:0] csr_bert_cfg2, // bert configuration bits output [15:0] csr_afe_tst_p1, output [15:0] csr_afe_tst_p2, output [15:0] csr_afe_tst_p3, output [15:0] csr_afe_tst_p4, output [47:0] csr_afe_tst_pc, output [47:0] csr_pll_tst, output [79:0] csr_pll_ctrl d148 1 a148 2 wire [15:0] reg_din; wire reg_write, reg_read; a155 59 reg [15:0] afe20_reg0_write, afe20_reg1_write, afe20_reg2_write, afe20_reg3_write, afe20_reg4_write, afe20_reg5_write, afe20_reg6_write, afe20_reg7_write, afe20_reg8_write, afe20_reg9_write, afe20_rega_write, afe20_regb_write, afe20_regc_write, afe20_regd_write, afe20_rege_write; reg [15:0] dfe20_reg0_write, dfe20_reg1_write, dfe20_reg2_write, dfe20_reg3_write, dfe20_reg4_write, dfe20_reg5_write, dfe20_reg6_write, dfe20_reg7_write, dfe20_reg8_write, dfe20_reg9_write, dfe20_rega_write; reg [15:0] afe30_reg0_write, afe30_reg1_write, afe30_reg2_write, afe30_reg3_write, afe30_reg4_write, afe30_reg5_write, afe30_reg6_write, afe30_reg7_write; reg [15:0] dfe30_reg0_write, dfe30_reg1_write, dfe30_reg2_write, dfe30_reg3_write, dfe30_reg4_write, dfe30_reg5_write, dfe30_reg6_write, dfe30_reg7_write, dfe30_reg8_write, dfe30_reg9_write, dfe30_rega_write, dfe30_regb_write, dfe30_regc_write, dfe30_regd_write, dfe30_rege_write, dfe30_regf_write, dfe30_regg_write, dfe30_regh_write, dfe30_regi_write, dfe30_regj_write; a168 48 parameter SYNC_TRACK = 1'b0, SKIP_ALIGN = 1'b0, SKIP_OVERRIDE = 1'b0, SKIP_MAXTH = 6'b00_1100, SKIP_HALFTH = 6'b00_0111, SKIP_MINTH = 6'b00_0111, LNKTRAINING = 1'b0, TXDISPARITYINIT = 1'b0, LFPS_CMPMAXTH = 8'hf3, // -13 LFPS_CMPMINTH = 8'h0d, // +13 LFPS_DEGLMAXTH = 3'b100, LFPS_DEGLMINTH = 3'b011, LFPS_WIDTH = 5'h02, // divide-by-4 LFCK_WIDTH = 16'h0014, // 20*Tref = 208.33ns @@ 96MHz ref clock SYMB_ERROR_MAX = 8'h0f, COMPPAT_WIDTH = 5'b0_1000, TIME_P1_ENTRY = 16'h000f, TIME_P2_ENTRY = 16'h000f, TIME_P3_ENTRY = 16'h000f, TIME_P1_EXIT = 16'h0025, // 25*8=200ns latency (25 pclks), rx latency is not accounted, it is about 1us TIME_P2_EXIT = 16'h00ff, TIME_P3_EXIT = 16'h0fff, TX_MARGDEMP_OVERRIDE = 1'b0, // tx margin and tx deemphasis mdio override TX_LPEN = 1'b0, TX_LSEN = 1'b0, REFCLKPD_P2ENABLE = 1'b0, // 1 -> refclk ckt is power-down when high in P2 REFCLKPD_P3ENABLE = 1'b1, // 1 -> refclk ckt is power-down when high in P3 TXPWRDN_P3ENABLE = 1'b1, // 1-> tx power-down is enabled during P3 RXTERM_TIMEOUT = 10'h040, PRBS_TXCLK2RXCLK = 1'b0, PRBS_RXERRCLR = 1'b0, PRBS_RXSTART = 1'b0, RLOOP_ENABLE = 1'b0, GLOOP_ENABLE = 1'b0, PRBS_ENABLE = 1'b0, PRBS_TXSTART = 1'b0, PRBS_ORDER = 2'b00, // 7th order (127-bits) PRBS_INV = 1'b0, PRBS_MODE = 1'b0, PRBS_WIDTH = 1'b1, // 10-bits PRBS_BURST = 1'b0, PRBS_SEED = 32'hffff_ffff, PRBS_PKT = 32'h0000_00ff, PRBS_SIZE = 16'h000a, PRBS_IPG = 16'h000f; d179 1 a179 1 `USB3_CKBUFX12 MDIO_CLK_tree_inst (.i(mdio_clk_scan), .o(mdio_clk)); d218 1 a218 1 `USB3_CKBUFX12 mdio_wrclk_tree_inst (.i(mdio_wrclk_scan), .o(mdio_wrclk)); @ 1.5 log @change reg_dout assignment for 1-port to only use dout[0] @ text @d13 3 d132 1 d499 1 d504 1 d514 1 @ 1.5.2.1 log @remove illegal `USB3_CKBUFX12 instances and replace with usb30_clkbuf make mdio_wrclk_delay_inst dont_touch so that it is not removed in synthesis @ text @a12 3 // Revision 1.5 2013/04/23 00:00:37 jerryp // change reg_dout assignment for 1-port to only use dout[0] // d384 1 a384 1 usb30_clkbuf MDIO_CLK_tree_inst (.i(mdio_clk_scan), .o(mdio_clk)); d419 1 a419 1 `USB3_DLY1000X3 mdio_wrclk_delay_inst_dont_touch (.i(reg_write), .o(reg_write_delay)); d423 1 a423 1 usb30_clkbuf mdio_wrclk_tree_inst (.i(mdio_wrclk_scan), .o(mdio_wrclk)); @ 1.5.2.2 log @change usb20_scan_pllmux instance to usb30_scan_pllmux @ text @a12 4 // Revision 1.5.2.1 2013/08/27 01:15:13 jerryp // remove illegal `USB3_CKBUFX12 instances and replace with usb30_clkbuf // make mdio_wrclk_delay_inst dont_touch so that it is not removed in synthesis // d377 1 a377 1 usb30_scan_pllmux u_usb30_scan_pllmux_MDIO (.i_func_clk (mdio_clk_i), @ 1.5.2.2..1 log @add sata and pcie register banks at 80c ad 80d @ text @a12 3 // Revision 1.5.2.2 2013/09/11 01:06:57 jerryp // change usb20_scan_pllmux instance to usb30_scan_pllmux // d124 1 a124 2 output [NUM_USB30_PORTS - 1:0] csr_mdio_sata_en, output [NUM_USB30_PORTS - 1:0] csr_mdio_pcie_en, d329 1 a329 2 SATA_BLOCK_ADDR = 12'h80c, PCIE_BLOCK_ADDR = 12'h80d, d488 1 a488 2 assign csr_mdio_sata_en[gi] = (base_addr_write[15:4] == SATA_BLOCK_ADDR + (gi * 12'h100)); // SATA block registers enable assign csr_mdio_pcie_en[gi] = (base_addr_write[15:4] == PCIE_BLOCK_ADDR + (gi * 12'h100)); // PCIE block registers enable @ 1.4 log @"Moved mdio_wrclk_tree_inst from output of MUX to i0 of MUX" @ text @d13 3 d487 2 d501 10 a510 1 @ 1.3 log @change (afe30, dfe30, rxpmd, txpmd)_dout inputs to support multiple pipes change reg_dout assignment to include dout from both pipe 0 and pipe 1 @ text @d13 4 a414 1 `USB3_CKMUX2X8 mdio_wrclk_scanmux_dont_touch (.i0(~reg_write), .i1(mdio_clk), .sel(scan_testmode), .o(mdio_wrclk_scan)); d416 5 a420 1 `USB3_DLY1000X3 mdio_wrclk_tree_inst (.i(mdio_wrclk_scan), .o(mdio_wrclk)); @ 1.2 log @add mdio_mode output so it can be used by vco_pllReg and other mdio blocks change csr_mdio_rxpmd_aeq_en block enable from one bit to two bits add SLCAL_BLOCK_ADDR and use it to enable csr_mdio_rxpmd_aeq_en[1] @ text @d13 5 d122 2 a123 2 input [15:0] csr_mdio_afe30_dout, input [15:0] csr_mdio_dfe30_dout, d128 1 a128 1 input [15:0] csr_mdio_rxpmd_dout, d132 1 a132 1 input [15:0] csr_mdio_txpmd_dout, d481 8 a488 4 csr_mdio_rxpmd_dout | csr_mdio_txpmd_dout | csr_mdio_afe30_dout | csr_mdio_dfe30_dout; @ 1.1 log @initial revision @ text @d12 4 a15 1 // $Log: usb30_phy_csr.v,v $ d90 1 d125 1 a125 1 output [NUM_USB30_PORTS - 1:0] csr_mdio_rxpmd_aeq_en, d311 2 a312 1 AEQ30_BLOCK_ADDR = 12'h80e; d459 2 a460 1 assign csr_mdio_rxpmd_aeq_en[gi] = (base_addr_write[15:4] == AEQ30_BLOCK_ADDR + (gi * 12'h100)); // AEQ30 block registers enable @