head	1.10;
access;
symbols;
locks; strict;
comment	@# @;


1.10
date	99.02.09.13.16.32;	author ryu;	state Exp;
branches;
next	1.9;

1.9
date	99.01.31.12.00.29;	author ryu;	state Exp;
branches;
next	1.8;

1.8
date	99.01.30.19.30.01;	author ryu;	state Exp;
branches;
next	1.7;

1.7
date	99.01.29.09.24.50;	author ryu;	state Exp;
branches;
next	1.6;

1.6
date	99.01.13.07.04.52;	author ryu;	state Exp;
branches;
next	1.5;

1.5
date	98.09.12.19.55.40;	author ryu;	state Exp;
branches;
next	1.4;

1.4
date	98.09.07.19.24.01;	author ryu;	state Exp;
branches;
next	1.3;

1.3
date	98.09.07.10.10.14;	author ryu;	state Exp;
branches;
next	1.2;

1.2
date	98.08.28.09.39.30;	author ryu;	state Exp;
branches;
next	1.1;

1.1
date	98.08.18.09.45.59;	author ryu;	state Exp;
branches;
next	;


desc
@# TODO:
@


1.10
log
@*** empty log message ***
@
text
@#	$Id: TODO,v 1.9 1999/01/31 12:00:29 ryu Exp ryu $

#	Copyright (C) 1999 Robert K. Yu
#	email: robert@@yu.org

#	This file is part of Autochar.

#	Autochar is free software; you can redistribute it and/or modify
#	it under the terms of the GNU General Public License as published by
#	the Free Software Foundation; either version 2, or (at your option)
#	any later version.

#	Autochar is distributed in the hope that it will be useful,
#	but WITHOUT ANY WARRANTY; without even the implied warranty of
#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#	GNU General Public License for more details.

#	You should have received a copy of the GNU General Public License
#	along with Autochar; see the file COPYING.  If not, write to the
#	Free Software Foundation, Inc., 59 Temple Place - Suite 330,
#	Boston, MA 02111-1307, USA.


x	Get port order from spice
	Get port direction from verilog

x	Handle differential, equivalent.

x	cin: optimization
x	setup/hold: use hspice bisect
x	    - look at internal node
	    - do not look at internal node
x	clock_q
	power
	path delay module (from static timing output)
	tristate buffer
	device characterization

x	Generate synopsys lib format
	Generate html datasheets

?	tcl GUI interface
-	Load defaults
	Error checking
	    spice run error, aborts
	    terminal existence check

x	Slew rate from exp source instead of slewbuffer.
x	Add resistor for buffer for inputcap.
	Setup/Hold using 5% deviation from idea clock-q time
	    as criterion.

x	slew rate dependence on setup/hold
x	output linear or nonlinear models (clock-q only)
x	index list for nonlinear models -> using lu_table_name


Key:
    x = done
    ? = propably not worth doing
    - = changed my mind
@


1.9
log
@*** empty log message ***
@
text
@d1 1
a1 1
#	$Id: TODO,v 1.8 1999/01/30 19:30:01 ryu Exp ryu $
d36 2
@


1.8
log
@*** empty log message ***
@
text
@d1 1
a1 1
#	$Id: TODO,v 1.7 1999/01/29 09:24:50 ryu Exp ryu $
d31 2
a32 1
x	    - optionally look at internal node
@


1.7
log
@added path delay module
@
text
@d1 1
a1 1
#	$Id: TODO,v 1.6 1999/01/13 07:04:52 ryu Exp ryu $
d34 1
a52 2

	path delay module
@


1.6
log
@header
@
text
@d1 1
a1 1
#	$Id$
d52 2
@


1.5
log
@update
@
text
@d1 22
a22 1
$Id: TODO,v 1.4 1998/09/07 19:24:01 ryu Exp ryu $
d25 1
a25 1
	Get port direction for verilog
d38 2
a39 2
	tcl GUI interface
	Load defaults
d42 1
a42 1
	    terminal existence
d52 6
@


1.4
log
@more things to do
@
text
@d1 1
a1 1
$Id: TODO,v 1.3 1998/09/07 10:10:14 ryu Exp $
d28 3
a30 3
	slew rate dependence on setup/hold
	output linear or nonlinear models
	index list for nonlinear models
@


1.3
log
@*** empty log message ***
@
text
@d1 1
a1 1
$Id$
d27 4
@


1.2
log
@*** empty log message ***
@
text
@d1 1
a1 1
# TODO:
d3 1
a3 1
	Get port order from spice
d17 1
a17 1
	GUI interface, either tcl or web.
d20 2
d23 2
a24 2
	Slew rate from piece-wise linear model instead of slewbuffer.
	Add resistor for buffer for inputcap.
d26 1
a26 1
	as criterion.
@


1.1
log
@entered into RCS
@
text
@d14 1
a14 1
	Generate synopsys lib format
d20 5
@