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1.2
date	99.01.28.07.01.02;	author ryu;	state Exp;
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1.1
date	99.01.21.06.18.41;	author ryu;	state Exp;
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.subckt nand2_2x in0 in1 out 

* Begin port declarations
* port input IN0
* port input IN1
* port output OUT
* End port declarations

mn0 out in0 n0 gnd nch w=10 l=0.35
mn1 n0 in1 gnd gnd nch w=10 l=0.35
mp2 out in0 vdd vdd pch w=10 l=0.35
mp3 out in1 vdd vdd pch w=10 l=0.35

c1 in0 gnd 10e-15 
c2 in1 gnd 10e-15 
c3 out gnd 20e-15 

.ENDS 
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@d2 1
a2 1
.SUBCKT NAND2_2X IN0 IN1 OUT 
d10 4
a13 4
MN0 OUT IN0 N0 GND NCH W=10 L=0.35
MN1 N0 IN1 GND GND NCH W=10 L=0.35
MP2 OUT IN0 VDD VDD PCH W=10 L=0.35
MP3 OUT IN1 VDD VDD PCH W=10 L=0.35
d15 3
a17 3
C1 IN0 GND 10e-15 
C2 IN1 GND 10e-15 
C3 OUT GND 20e-15 
@