- head 1.16;
- access;
- symbols;
- locks; strict;
- comment @-- @;
-
-
- 1.16
- date 99.07.28.14.55.42; author ryu; state Exp;
- branches;
- next 1.15;
-
- 1.15
- date 99.01.14.10.18.22; author ryu; state Exp;
- branches;
- next 1.14;
-
- 1.14
- date 99.01.13.07.25.40; author ryu; state Exp;
- branches;
- next 1.13;
-
- 1.13
- date 98.09.12.19.54.34; author ryu; state Exp;
- branches;
- next 1.12;
-
- 1.12
- date 98.09.08.12.28.50; author ryu; state Exp;
- branches;
- next 1.11;
-
- 1.11
- date 98.09.01.04.26.37; author ryu; state Exp;
- branches;
- next 1.10;
-
- 1.10
- date 98.08.30.19.23.36; author ryu; state Exp;
- branches;
- next 1.9;
-
- 1.9
- date 98.08.29.17.28.35; author ryu; state Exp;
- branches;
- next 1.8;
-
- 1.8
- date 98.08.26.09.36.46; author ryu; state Exp;
- branches;
- next 1.7;
-
- 1.7
- date 98.08.24.00.49.12; author ryu; state Exp;
- branches;
- next 1.6;
-
- 1.6
- date 98.08.23.22.11.09; author ryu; state Exp;
- branches;
- next 1.5;
-
- 1.5
- date 98.08.18.09.32.38; author ryu; state Exp;
- branches;
- next 1.4;
-
- 1.4
- date 98.08.17.02.40.23; author ryu; state Exp;
- branches;
- next 1.3;
-
- 1.3
- date 98.08.16.11.58.20; author ryu; state Exp;
- branches;
- next 1.2;
-
- 1.2
- date 98.08.15.09.08.49; author ryu; state Exp;
- branches;
- next 1.1;
-
- 1.1
- date 98.08.15.07.11.30; author ryu; state Exp;
- branches;
- next ;
-
-
- desc
- @#! /usr/local/bin/perl
- @
-
-
- 1.16
- log
- @checking in
- @
- text
- @# $Id: load_delay.spec,v 1.15 1999/01/14 10:18:22 ryu Exp ryu $
-
- # Copyright (C) 1999 Robert K. Yu
- # email: robert@@yu.org
-
- # This file is part of Autochar.
-
- # Autochar is free software; you can redistribute it and/or modify
- # it under the terms of the GNU General Public License as published by
- # the Free Software Foundation; either version 2, or (at your option)
- # any later version.
-
- # Autochar is distributed in the hope that it will be useful,
- # but WITHOUT ANY WARRANTY; without even the implied warranty of
- # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- # GNU General Public License for more details.
-
- # You should have received a copy of the GNU General Public License
- # along with Autochar; see the file COPYING. If not, write to the
- # Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- # Boston, MA 02111-1307, USA.
-
- #------ LOAD DELAY CHARACTERIZATION --------------------------------------------
-
-
- #-------------------------------------------------------------------------------
- # The syntax are the same as the Perl language. Any
- # valid Perl expression can be used. In fact, this file is
- # executed directly, so the order of the definitions is
- # important: Be sure the '&autochar' command, which is actually
- # a subroutine call to the function 'autochar', is called after
- # the necessary definitions are made.
- #-------------------------------------------------------------------------------
-
- # Any of the global defaults may be changed here. See
- # $AUTOCHAR/lib/defaults.pl for a list of what they are.
-
- # $spice_cmd = 'hspice';
- # $techpath = '/path/to/spice/libraries';
- # $spice_corner = 'hspice.ttlh';
- # $spice_include = '.include /some/special/include.file';
- # $scale_cload = 0.66e-15;
- # $scale_delay = 0.060e-9;
- # $trans_period = '2ns';
- # etc.
-
-
- #-------------------------------------------------------------------------------
- # Specify the characterization type.
-
- $sim_type = 'load_delay';
-
-
- #-------------------------------------------------------------------------------
- # Specify the name of the spice subckt and the file containing
- # the spice subckt.
-
- $cellname = 'nand3_8x';
- $spice_netlist = 'nand3_8x.sp';
-
-
- #-------------------------------------------------------------------------------
- # List of the terms to the cell. Order is unimportant.
- # Each name is prefixed by a ":x" letter to indicate type:
- # :i = input
- # :o = output
- # :b = biput
- # :v = vdd supply
- # :g = gnd
-
- # Declare the list manually
- @@termlist = (
- 'in0:i',
- 'in1:i',
- 'in2:i',
- 'out:o',
- );
-
-
- # Alternatively, get the term definition from other netlist.
- # @@termlist = &read_spice_terms ("filename", $cellname);
-
-
- #-------------------------------------------------------------------------------
- # Vary the slewrate of the input being characterized.
- # @@slewrate = &vary_list(<start>, <incr>, <N>, <units>);
- # @@slewrate = &vary_list(500, 200, 3, '');
-
- # Or specify the explicit list of slewrate values
- # @@slewrate = (0.66667, 1.33333, 2, 2.66667, 5.3333);
-
-
- #-------------------------------------------------------------------------------
- # Define input buffers. The name of the buffer is a two-port subckt
- # that will be placed between the input pulse source and the input
- # term being characterized. Typically, this is a buffer of some sort.
- # If 'none' is specified, then no buffer will be added.
-
- $buffer{'default'} = 'buf_3x';
- # $buffer{'in2'} = 'buf_4x';
- # $buffer{'in3'} = 'none';
-
- # Special slewrate buffer
- $buffer{'default'} = 'slewbuf';
-
-
- # Define any special differential inputs. For example,
- # in0 and in1 are defined as a differential input pair,
- # with in1 being the reference.
- # $differential{'in0'} = 'in1';
-
- # Define any special differential inputs. For example,
- # in0 and in1 are defined as a differential input pair,
- # with in1 being the reference.
- # $differential{'in0'} = 'in1';
-
- # Define any special equivalent inputs. For example,
- # in0 and in1 are defined as a equivalent input pair,
- # with in1 being the reference.
- # $equivalent{'in0'} = 'in1';
-
-
- #-------------------------------------------------------------------------------
- # Define the output loads.
-
- # Vary the cload to the output being characterized.
- # @@cload = &vary_list(<start>, <incr>, <N>, <units>);
- @@cload = &vary_list(10, 10, 5, 'ff');
-
- # Or specify the explicit list of cload values
- # @@cload = ('1fF', '100fF', '300fF');
-
- # Specify the loads for the output(s) that are not being characterized.
- # If 'none' is specified, then no output loading is added. Use
- # the words 'cap:', 'res:', or 'subckt:' to indicate an output load that
- # is an ideal capacitor, an ideal resistor, or a one-port spice subckt.
-
- $load{'default'} = 'none';
- # $load{'out1'} = 'cap:10ff';
- # $load{'out1'} = 'res:1K';
- # $load{'out1'} = 'subckt:buf_4x';
-
-
- #-------------------------------------------------------------------------------
- # Characterization command. The general form is:
- # &autochar ( <type>, <input>, <output>, [ <tie>, <unused>+ ]);
- #
- # <type> = type of characterization.
- # The valid types are:
- #
- # inverting : both tplh and tphl are characterized
- # assuming <output> is an inverting output w.r.t. <input>
- #
- # non_inverting : both tplh and tphl are characterized
- # assuming <output> is an non-inverting output
- # w.r.t. <input>
- #
- # hh : tplh only with rising <input>
- # hl : tphl only with rising <input>
- # lh : tplh only with falling <input>
- # ll : tphl only with falling <input>
- #
- # <input> = exact name of the input to characterize
- # <output>= exact name of the output to characterize
- #
- # optional:
- # <tie> = how to tie the other inputs, either 'tie_high' or 'tie_low'
- # <unused>= name(s) of the inputs to be tied. These are regular
- # perl expresssions. Be sure to write brackets [ and ]
- # as \[ and \], respectively.
- #
-
- &autochar ('inverting', 'in0', 'out', tie_high, '.*');
- &autochar ('inverting', 'in1', 'out', tie_high, '.*');
- &autochar ('inverting', 'in2', 'out', tie_high, '.*');
-
-
- #-------------------------------------------------------------------------------
- # In some cases, it is desirable to skip the characterization of certain arcs
- # and to copy the data from another set of arcs instead. The general form is:
- # ©char (<input>, <output>, <ref_input>, <ref_output>);
-
- # ©char ('in0', 'out', 'in1', 'out');
-
-
- # Must return a value to make perl happy.
- 1;
- @
-
-
- 1.15
- log
- @Using /usr/bin/perl
- @
- text
- @d1 1
- a1 3
- #! /usr/bin/perl
-
- # $Id: load_delay.spec,v 1.14 1999/01/13 07:25:40 ryu Exp ryu $
- @
-
-
- 1.14
- log
- @GPL
- @
- text
- @d1 1
- a1 1
- #! /usr/local/bin/perl
- d3 1
- a3 1
- # $Id$
- @
-
-
- 1.13
- log
- @Simplified parameters; got rid of @@init, @@trans
- @
- text
- @d3 1
- a3 5
- # Copyright (c) 1998-2001, Robert K. Yu. All Rights Reserved.
- #
- # No part of this program may be used, reproduced, stored in a
- # retrieval system, or transmitted in any form or by any
- # means without the prior permission of the author.
- d5 2
- a6 3
- # $Id: load_delay.spec,v 1.12 1998/09/08 12:28:50 ryu Exp ryu $
- # Autochar Specification File
- # Author: Robert K. Yu
- d8 16
- @
-
-
- 1.12
- log
- @copyright notice
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.11 1998/09/01 04:26:37 ryu Exp ryu $
- d29 7
- a35 7
- # $init{'spice_cmd'} = 'hspice';
- # $init{'techpath'} = '/path/to/spice/libraries';
- # $init{'corner'} = 'hspice.ttlh';
- # $init{'include'} = '.include /some/special/include.file';
- # $init{'scale_cload'} = 0.66e-15;
- # $init{'scale_delay'} = 0.060e-9;
- # $trans{'period'} = '2ns';
- a72 1
- # @@termlist = &read_verilog_terms ("filename", $cellname);
- d76 1
- a76 3
- # Vary the slewrate of the input being characterized. Be
- # sure to use the 'slewbuffer' to make use of these values;
- # The units of the 'slewbuffer' are unitless gate delays.
- @
-
-
- 1.11
- log
- @read_spice_terms
- @
- text
- @d3 1
- a3 1
- # Copyright (c) 1998, Robert K. Yu. All Rights Reserved.
- d9 1
- a9 1
- # $Id: load_delay.spec,v 1.10 1998/08/30 19:23:36 ryu Exp ryu $
- @
-
-
- 1.10
- log
- @Renamed port to term
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.9 1998/08/29 17:28:35 ryu Exp ryu $
- d71 2
- a72 1
- # Alternatively, get the term definition from verilog netlist.
- @
-
-
- 1.9
- log
- @1.3
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.8 1998/08/26 09:36:46 ryu Exp ryu $
- d54 1
- a54 1
- # List of the ports to the cell. Order is unimportant.
- d63 1
- a63 1
- @@portlist = (
- d71 2
- a72 2
- # Alternatively, get the port definition from verilog netlist.
- # @@portlist = &read_verilog_ports ("filename", $cellname);
- d89 1
- a89 1
- # port being characterized. Typically, this is a buffer of some sort.
- @
-
-
- 1.8
- log
- @Added slew rate modelling.
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.7 1998/08/24 00:49:12 ryu Exp $
- d77 4
- a80 4
- # sure to use the 'slewbuf' to make use of these values;
- # The units of the 'slewbuf' are unitless gate delays.
- # @@slewrate = &vary_slewrate(<start>, <incr>, <N>, <units>);
- # @@slewrate = &vary_slewrate(500, 200, 3, '');
- d120 2
- a121 2
- # @@cload = &vary_cload(<start>, <incr>, <N>, <units>);
- @@cload = &vary_cload(10, 10, 5, 'ff');
- @
-
-
- 1.7
- log
- @Added copychar syntax
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.6 1998/08/23 22:11:09 ryu Exp ryu $
- d76 11
- d93 1
- a93 1
- $buffer{'in2'} = 'buf_4x';
- d96 3
- d124 1
- a124 1
- # @@cload = ('10ff', '20ff', '30ff');
- @
-
-
- 1.6
- log
- @Robert K. Yu
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.5 1998/08/18 09:32:38 ryu Exp ryu $
- d155 8
- @
-
-
- 1.5
- log
- @Changed default corner.
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.4 1998/08/17 02:40:23 ryu Exp ryu $
- d11 1
- a11 1
- # Author: Robert Yu
- @
-
-
- 1.4
- log
- @Clean up.
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.3 1998/08/16 11:58:20 ryu Exp ryu $
- d31 1
- a31 1
- # $init{'corner'} = 'hspice.tthl';
- d125 1
- a125 1
- # &autochar ( <type>, <input>, <output>, <tie>, <unused>+);
- d144 2
- @
-
-
- 1.3
- log
- @changed syntax.
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.2 1998/08/15 09:08:49 ryu Exp ryu $
- d56 5
- a60 5
- # .i = input
- # .o = output
- # .b = biput
- # .v = vdd supply
- # .g = gnd
- @
-
-
- 1.2
- log
- @entered into RCS
- @
- text
- @d9 1
- a9 1
- # $Id: load_delay.spec,v 1.1 1998/08/15 07:11:30 ryu Exp ryu $
- d137 4
- a140 4
- # ^^ : tplh only with rising <input>
- # ^v : tphl only with rising <input>
- # v^ : tplh only with falling <input>
- # vv : tphl only with falling <input>
- @
-
-
- 1.1
- log
- @entered into RCS
- @
- text
- @d9 1
- a9 1
- # $Id: spec.pl,v 1.2 1998/08/13 07:29:36 ryu Exp ryu $
- d13 1
- d16 1
- d40 1
- a40 4
- # Specify the characterization type. Available types are:
- # load_delay
- # input_cap
- # setup_hold
- a42 2
- # $sim_type = 'input_cap';
- # $sim_type = 'setup_hold';
- @